A NAND flash memory has a plurality of memory cells arranged in a row direction and connected to a write and read latch circuit via bit lines and data is simultaneously written or read with respect to the memory cells arranged in the row direction.
Further, in the NAND flash memory, the source and drain diffusion layers of a plurality of memory cells arranged in a column direction are serially connected to configure a NAND string and the NAND string is connected to a bit line through a via.
However, recently, it becomes more difficult to form vias used for connecting the NAND strings to the bit lines as a device becomes more miniaturized.